The present invention relates to a low power consumption charge pump circuit.
Specifically, the invention relates to a charge pump circuit that is connected between a first voltage reference and an output terminal.
The invention further relates to a method of generating a substantially constant voltage signal whose value exceeds a supply voltage reference.
The invention relates, particularly but not exclusively, to a charge pump circuit for low power applications, this description covering that field for convenience of illustration only.
As is well known, extensive use is made nowadays of nonvolatile digital data memory devices. Consumer products, such as still and TV cameras, xe2x80x9cwalkmen,xe2x80x9d cellular phones, and electronic notebooks, require this kind of memory devices for storing information in a compact support of large capacity.
A shortcoming of nonvolatile memory devices is the high power consumption that associates with their operation. This is obviously of major consequence to portable products like those listed above, which have to be battery powered.
Most of the power expended to operate such memories goes to charge pump circuits, which are arranged to raise the voltage value above the supply (usually, battery) level for further supplying a part of the circuitry integrated in the memory device. This is because the voltages needed to perform such basic operations as program and erase operations in nonvolatile memory devices, and in low voltage supply circuits read operations as well, are higher than the supply voltage.
Thus, providing charge pump circuits that would absorb as little as possible on the power supply for their operation is quite important, and the present trend toward ever lower supply voltages for integrated circuits can only emphasize this importance.
A standard charge pump circuit for nonvolatile memory chips is shown in FIG. 1, that illustrates a known charge pump of the Dickson type.
This charge pump comprises a plurality of stages S1-SN, which are connected in cascade between an input node that is connected to a voltage supply line VDD, and an output node. The output node is connected to a load L represented by a capacitor having a capacitance CL and being connected in parallel with a current-absorbing element IOUT connected between said output node and a reference GND. Each stage comprises a charge transfer element PS comprising of a pass transistor that has its gate terminal driven by appropriate drive signals, and a transfer capacitor of capacitance CT having one plate connected to the transfer element PS and the other plate connected to a drive signal A, B, C, D.
Two equations are related with the circuit of FIG. 1 which link the circuit output voltage VOUT and the current IIN absorbed from the supply reference to variation of the current IOUT that the circuit is to supply to the load:                               V          OUT                =                                                            (                                  n                  +                  1                                )                            ⁢                              V                DD                                      -                          n              ⁢                                                I                  OUT                                                  f                  ⁢                                      xe2x80x83                                    ⁢                                      C                    T                                                                                =                                    V                              OUT                ,                MAX                                      -                                          R                OUT                            ⁢                              I                OUT                                                                        (        1        )            xe2x80x83IIN=(n+1)IOUT+nƒCPARVDDxe2x80x83xe2x80x83(2)
where:
n is the number of stages used in the charge pump;
IOUT is the output current, i.e., the current absorbed from the load;
VDD is the supply voltage;
CT is the capacitance of the transfer capacitors;
CPAR is the capacitance of a parasitic capacitor of the bottom plate of each transfer capacitor; and
ƒ is the frequency of the clock signal (i.e., the switching frequency of the drive signals A, B, C, D to the charge pump).
The single parasitic effect considered in equation (2) is that due to the parasitic capacitance that exists between the bottom plates of the transfer capacitors of capacitance CT and the ground reference GND. This, of course, is inclusive of the parasitic capacitance of the lines connected to this plate, which capacitance is usually much lower than the parasitic capacitance of the plate itself. In particular, the parasitic capacitances associated with the internal nodes of the charge pump, such as the capacitance of the top plates of the capacitors and the parasitic capacitances associated with the capacitors Cg and the other charging elements PS, are neglected in Equations (1) and (2).
In particular, it is evinced from Equation (1) that the loadless output voltage VOUT,MAX, i.e., the current absorbed from the load L is zero, of the charge pump is VOUT,MAX=(n+1)VDD, and the loadless output resistance ROUT is n/ƒCr.
Equation (1) shows that. if a current IOUT is to be delivered with the output voltage VOUT held at or above a predetermined value, a minimum of stages must be used. Also, to minimize the voltage drop due to the charge pump circuit delivering the current IOUT, a high frequency and large transfer capacitors must be used.
However, the last-mentioned requirement collides with the provisions of Equation (2) because, as the capacitance CT of the transfer capacitors increases, the value CPAR of the parasitic capacitances also increases, and with it the current IIN absorbed from the power supply. The same consideration applies to the frequency ƒ.
Accordingly, the charge pump circuits are at once required to deliver the necessary current to the load, to hold the output voltage at an adequate level, and to absorb the lowest possible amount of current IIN from the power supply.
This is particularly true when the charge pump is used for driving a load whose absorption of the current IOUT varies conspicuously with time. To provide a desired value of the output voltage VOUT at a large value of the current IOUT, the product ƒCT has to be sufficiently high. With such a pump, when the current IOUT absorbed from the load is small, the output voltage VOUT approaches its maximum VOUT,MAX (corresponding to the loadless voltage value). The drop due to the term IOUT/ƒCT is thus minimized.
Under these conditions, the voltage value VOUT is high, although a lower output voltage value VOUT would be sufficient to ensure proper performance of the whole circuit. Thus, it makes no sense to keep the charge pump at the top of its capacity under such conditions, while it could be operated at lower levels and reduced power absorbed from the power supply, i.e., at a lower value of ƒCT.
A first prior approach to reach this requirement provides for on/off control of the output voltage VOUT, i.e., the charge pump turns off as soon as the output voltage reaches a higher preset threshold value, and turns on again as the output voltage falls below this value.
Despite its simple design, this approach has a drawback in that, at each working cycle of the drive signals, a predetermined charge amount xcex94Q is output. As said before, if the charge pump circuit is sized to provide a desired output voltage level VOUT when there is a high output current IOUT, the charge amount xcex94Q will be adequately large, because the charge amount xcex94Q equals the amount of charge absorbed by the load L during one cycle of the drive signals A-D. Thus, as the control loop by which the charge pump is turned on/off operates the charge pump, the output voltage VOUT will experience a manifest increase. This increase is then cancelled, in time interval, by the absorption from the load L. This produces substantial rippling of the output voltage VOUT.
The ripple is the more manifest when some delay occurs in the control loop. In this case, the charge pump may stay xe2x80x98onxe2x80x99 for some time even if the output voltage VOUT exceeds the preset threshold level, so that the ripple amplitude is increased.
A prior embodiment based on the on/off control technique provides for the capacitance CT of the transfer capacitors to vary with the current IOUT absorbed from the load. This requires the availability of a DPCA (Digital Programmable Capacitor Array), i.e., sets of cascaded capacitors adapted for independent activation. However, where high operating voltages are involved, high-voltage capacitors must be used, i.e., capacitors that can withstand large electric fields between their plates. By reason of their construction, such capacitors exhibit large parasitic capacitances between their bottom plates and ground. With the bottom plates of the capacitors connected to the drive signals, this leads to a large dissipation of power according to Equation (2). Also, the connection of the bottom plate to the internal node of the charge pump causes the capacitive partition ratio of the individual stages to be exceedingly low, thus draining a significant portion of the charge on the internal nodes of the charge pump to ground and reducing the maximum attainable value VOUT,MAX of the output voltage.
Furthermore, high-voltage switches must be provided for selecting the DPCA capacitors, these switches taking up a large amount of silicon area and having large parasitic capacitances.
A second prior approach to the problem of controlling power consumption of the charge pump provides for the output voltage to be controlled by adjusting the frequency of the clock signal.
However, not even this approach is devoid of shortcomings, although it does provide a smoother output voltage. Since the capacitance CT of the transfer capacitor must be large when the current absorption from the load L is small, the output voltage VOUT is once again rippled (due to that the charge amount xcex94Q may be too large during a single cycle of the drive signals).
The underlying technical problem of this invention is to provide a charge pump circuit with appropriate structural and functional features to lower power consumption both in operation and standby, i.e., when no current is absorbed by the charge pump output (standby), thereby overcoming the drawbacks that beset prior art circuits.
The resolutive idea which is at the basis of this invention is that of providing a charge pump that comprises a parallel of at least two elementary charge pump circuits, wherein the charge pump is able to sense the current IOUT absorbed from the load connected thereto, and accordingly select the best combination of elementary charge pump circuits for each absorbed current IOUT.
Based on this principle, the technical problem is solved by a circuit as indicated, and as defined in claim 1.
The problem is further solved by a method as previously indicated, and as defined in claim 10.
The features and advantages of the device according to the invention will be apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.